//Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2018.2 (lin64) Build 2258646 Thu Jun 14 20:02:38 MDT 2018
//Date        : Fri Aug 23 15:48:39 2019
//Host        : zw-pc running 64-bit Ubuntu 16.04.3 LTS
//Command     : generate_target ultra96v2_wrapper.bd
//Design      : ultra96v2_wrapper
//Purpose     : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

module ultra96v2_wrapper
   (BT_ctsn,
    BT_rtsn,
    can_phy_rx_0,
    can_phy_tx_0);
  input BT_ctsn;
  output BT_rtsn;
  input can_phy_rx_0;
  output can_phy_tx_0;

  wire BT_ctsn;
  wire BT_rtsn;
  wire can_phy_rx_0;
  wire can_phy_tx_0;

  ultra96v2 ultra96v2_i
       (.BT_ctsn(BT_ctsn),
        .BT_rtsn(BT_rtsn),
        .can_phy_rx_0(can_phy_rx_0),
        .can_phy_tx_0(can_phy_tx_0));
endmodule
